The present invention relates to a semiconductor memory device in which a capacity element is used as a memory cell.
Recently, the integration of a semiconductor memory device has increased, and accordingly, the semiconductor memory device, which results in subsequent chip size of the semiconductor memory device has increased. Such an increase in chip size may cause longer wiring lengths, and the wiring resistance may greatly affect the semiconductor memory device in high-speed and stable operations.
FIG. 6 is a block diagram showing a substantial part of a conventional semiconductor memory device.
Referring to FIG. 6, a description of the data read-out operation follows. A row address signal latched by a row address buffer 1 is decoded by a row decoder 2. A specific word line in a memory cell array 4 in which a number of memory cells are arranged in the shape of a matrix is activated by the output signal of a word line driver 3.
As a result, data from a plurality of memory cells connected to the activated word line is read out via a plurality of data lines 5 into a sense amplifier 6. The read-out data is amplified by the sense amplifier 6 which is driven by a sense amplifier driver 7, and then fed to a data selector 8. On the other hand, column address signals latched by a column address buffer 9 are decoded by a column decoder 10. The data fed to the data selector 8 is transmitted to a data output buffer 11 in response to the output of a column decoder 10, and output data is delivered from the data output buffer 11.
FIG. 7 is a schematic circuit diagram of part of the memory array 4, the sense amplifier 6 and the sense amplifier driver 7. As shown in FIG. 7, the data lines 5-1-5-5 are constituted by a pair of signal lines respectively, and memory cells 13 consisting of capacity elements are connected between one signal line of the respective data lines 5-1-5-5 and word line 12 (FIG. 7 shows only one memory cell 13). The sense amplifier 6 is comprised of a plurality of differential amplifiers 14-18 each connected to the data lines 5-1-5-5. The differential amplifiers 14-18 each have a pair of control terminals, one of which is connected to a restore signal line 19 and another to a drive signal line 20. R1 designates the resistance of the restore signal line 19 and drive signal line 20. The restore signal line 19 has one end connected to a p-type field effect transistor 21 and the drive signal line 20 has one end connected to an n-type field effect transistor 22. The sense amplifier driver 7 is constituted by these transistors 21 and 22. A drive signal which actuates the sense amplifier 6 is applied to the input terminals 23 and 24 of the sense amplifier driver 7. The differential amplifiers 14-18 are constituted, as specified by the differential amplifier 15, by a pair of n-type field effect transistors and a pair of p-type field effect transistors.
FIG. 8 shows voltages waveforms produced in the operation of the conventional semiconductor memory devices as shown in FIGS. 6 and 7. The abscissa axis represents time. The change of potential of the data lines 5-1-5-5 connected to the differential amplifiers 14-18 can be viewed with respect to the areas A and B in FIG. 8. The area A shows the change of potential when the data lines 5-1-5-5 are connected to the memory cells 13. In this area, the differential amplifiers 14-18 do not operate yet. The potentials of the data lines 5-1-5-5 vary with the state (0-1) of the data stored in the memory cells 13. If the data is "0", the potential of one signal line of the pair of data lines will become negative with respect to a half potential of a source voltage Vcc. If the data is "1", the potential will be positive. The area B shows the potential change after the differential amplifiers 14-18 have operated. In the area B, the voltage at the input terminal 24 of the sense amplifier driver 7 rises from the ground level, and the transistor 22 turns on. As a result, the drive signal line 20 will be grounded, so that all the differential amplifiers 14-18 will operate. Consequently, the potential of the lower voltage signal line of each pair of data lines is pulled down to the ground level. On the other hand, the voltage level at the input terminal 23 of the sense amplifier driver 7 will reach the ground level, and the transistor 21 turns on. Consequently, the potential of the higher voltage signal line of each pair of data lines is pulled up to the source voltage Vcc.
With such a conventional semiconductor memory device, however, there lies a problem in that high speed and stable operation can not be expected when the chip size becomes large due to the increase in the number of memory cells and the resultant increase in the length of the wiring.
FIG. 9 shows the potential change under the condition that only one of the differential amplifiers 14-18 amplifies the data "0" and all the rest differential amplifiers amplify the data "1". In FIG. 9, 25 identifies a potential change of the data line when the data "0" is read out, and 26 is a potential change of the data line when the data "1" is read-out. Elements 27 and 28 are a potential change of the drive signal line 20; it is shown that the wiring resistance R1 has a small value at 27 and that the wiring resistance R1 has a great value at 28.
As is apparent from curves 25 and 26 in FIG. 9, before operating the differential amplifiers 14-18, the potential of the data line of data "1" rises rapidly, while the potential of the data line of data "0" rises slowly. The differential amplifiers 14-18 start their operation when the potential of drive signal line 20 drops to the value which the potential difference between the higher voltage signal line of a pair of data lines and the drive signal line 20 becomes equal to a threshold voltage Vo. In FIG. 9, the differential amplifier starts amplification of data "1" at the time A. At this time, the wiring resistance R1 of the drive signal line 20 is small, the differential amplifier instantly starts amplification of data "0". However, if the wiring resistance R1 is large, all differential amplifiers 14-18 operate simultaneously, and thus, a great deal of instantaneous electrical current flows. This causes a potential drop at the drive signal line 20, so that there will be a timing delay in the lowering of a drive signal as shown by the curve 28 despite the fact that there should be an inherent variation as shown by the curve 27. As a result, the operation start timing of the differential amplifiers for amplifying the data at state "0" moves from the point A to the point B. If such a delay increases, it becomes difficult to transmit the data correctly to a following circuit.
The pair of n-type field effect transistors perform operations dominantly in the differential amplifiers 14-18 as shown in FIG. 7. Thus, as in FIG. 9, when a single differential amplifier serves to amplify the data "0" and all the remaining differential amplifiers serve to amplify the data "1", a delay of the operation start timing will become significant.